Critically discuss the particular determinants of demand for Toyota Motor Corporation Global benchmarking them against the theory. The determinants include: - Price, Income, Prices of Related Products,...4. Assessment on this module4.1.1 Element 010– ASSIGNMENT 3000 WORDS (100%)Element Type of assessment Word ortime limit % of Total Mark Submission method Final Submission Date010 ASSIGNMENT 3000 WORDS...ASSESSMENT BRIEFSubject Code and Title ACCT6007 Financial Accounting Theory and PracticeAssessment Critical AnalysisIndividual/Group IndividualLength 1500 words +/- 10%Learning Outcomes 1. Identify the...Unit 4 QuestionsST. MARY'S CATHOLIC COLLEGEProviding excellence in Education since 1986YEAR 12 AUTHORITY ENGLISHTASK 1: PUBLIC PERSUASIVE SPEECHUNIT 1: VOICES FROM THE PASTNAME: M(1-1,q),e, Vat-) Oe,r Krr,00 CLASS:...Key AssignmentUtilizing any available disclosed database for SPSS, develop a researchable set of hypotheses related to the database. Clearly define quantitatively analyzable hypotheses, analyze your data...Unit Quiz and Unit Homework as attached**Show All Questions**

Answer the following questions in your own words. This assignment covers Chapter 1, and Appendices A, B and C.

1. Consider the following sequence of instructions (the first register is the destination, except in the sw instruction, where the first register is the source):

S1: lw R6, 0(R2)

S2: lw R7, 0(R1)

S3: add R4, R6, R7

S4: mul R6, R7, 2

S5: sw R4, 0(R3)

Identify the dependencies in this set of instructions. Specify the instructions involved and the register.

2. Write the DLX code that performs the following arithmetic:

B * C + C / D + A

3. Suppose that a pipeline processor has 8 stages. The stage latencies (completion times) are: 30,40, 50, 10, 10, 30, 20, 50. These times are nanoseconds. The interstage register overhead is5ns.

i. What should the pipeline cycle time be, included the overhead?

ii. Suppose a non-pipelined processor used the stage logic to execute instructions serially (one at a time, with no register overhead). How long would it take the non-pipeline processor to complete 1000 instructions?

iii. How long would it take the pipelined processor to complete 1000 instructions?

iv. What is the speedup of the pipelined processor over the non-pipelined processor?

4. Suppose that a system executes 1,000,000 instructions. The program has the following distribution: 30% load/store instructions, 50% ALU (integer) instructions, 15% branch instructions, and 5% floating point instructions. The CPI for each category of instruction is: load/store-3, ALU-1, branch-4, floating point-8.

i. What is the execution time of the program?

ii. Suppose that the CPI of the floating point program is reduced by half. What is the speed up on the new system over the old?

5. Suppose that a program spends 80% of its time doing I/O through the system hard drive and 20% executing instructions. Using Amdahl's Law, calculate the speedup if you replaced the current hard drive with one that is 1.25 times faster. Calculate the speedup if you replaced the CPU (which executes the instructions) with one twice as fast. Which gives you that better speedup?

6. Write three short assembly language programs in the DLX code. These assembly language programs will do the following:

• compute the average of 10 numbers in memory and store the result to memory

• compute the greatest common divisor of two numbers in memory and store the result to memory

• compute the inner product of two five element vectors

1. Consider the following sequence of instructions (the first register is the destination, except in the sw instruction, where the first register is the source):

S1: lw R6, 0(R2)

S2: lw R7, 0(R1)

S3: add R4, R6, R7

S4: mul R6, R7, 2

S5: sw R4, 0(R3)

Identify the dependencies in this set of instructions. Specify the instructions involved and the register.

2. Write the DLX code that performs the following arithmetic:

B * C + C / D + A

3. Suppose that a pipeline processor has 8 stages. The stage latencies (completion times) are: 30,40, 50, 10, 10, 30, 20, 50. These times are nanoseconds. The interstage register overhead is5ns.

i. What should the pipeline cycle time be, included the overhead?

ii. Suppose a non-pipelined processor used the stage logic to execute instructions serially (one at a time, with no register overhead). How long would it take the non-pipeline processor to complete 1000 instructions?

iii. How long would it take the pipelined processor to complete 1000 instructions?

iv. What is the speedup of the pipelined processor over the non-pipelined processor?

4. Suppose that a system executes 1,000,000 instructions. The program has the following distribution: 30% load/store instructions, 50% ALU (integer) instructions, 15% branch instructions, and 5% floating point instructions. The CPI for each category of instruction is: load/store-3, ALU-1, branch-4, floating point-8.

i. What is the execution time of the program?

ii. Suppose that the CPI of the floating point program is reduced by half. What is the speed up on the new system over the old?

5. Suppose that a program spends 80% of its time doing I/O through the system hard drive and 20% executing instructions. Using Amdahl's Law, calculate the speedup if you replaced the current hard drive with one that is 1.25 times faster. Calculate the speedup if you replaced the CPU (which executes the instructions) with one twice as fast. Which gives you that better speedup?

6. Write three short assembly language programs in the DLX code. These assembly language programs will do the following:

• compute the average of 10 numbers in memory and store the result to memory

• compute the greatest common divisor of two numbers in memory and store the result to memory

• compute the inner product of two five element vectors